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The work reported in ``Granular micromechanics-based identification of isotropic strain gradient parameters for elastic geometrically nonlinear deformations" misidentified key terms in the grain-pair objective relative displacement when accounting for the second gradient of placement. In this paper, we correct that oversight by deriving a revised expression for the grain-pair objective relative displacement within the granular micromechanics framework. The amended terms, which resemble Christoffel symbols expressed in terms of strain gradients, modify the contributions of both the normal and tangential components to the strain energy and, consequently, alter the identified strain gradient elastic parameters. Importantly, the identification of the standard (first gradient) elastic tensor remains unchanged. This brief paper presents the corrected derivation, the resulting stiffness tensors for anisotropic strain gradient elasticity, and updated analytical expressions for the material parameters in both 2D and 3D isotropic settings. 

Deep Neural Networks (DNNs) have been successfully applied in many fields. Considering performance, flexibility, and energy efficiency, Field Programmable Gate Array (FPGA) based accelerator for DNNs is a promising solution. The existing frameworks however lack the possibility of reusability and friendliness to design a new network with minimum efforts. Modern high-level synthesis (HLS) tools greatly reduce the turnaround time of designing and implementing complex FPGA-based accelerators. This paper presents a framework for hardware accelerator for DNNs using high level specification. A novel architecture is introduced that maximizes data reuse and external memory bandwidth. This framework allows to generate a scalable HLS code for a given pre-trained model that can be mapped to different FPGA platforms. Various HLS compiler optimizations have been applied to the code to produce efficient implementation and high resource utilization. The framework achieves a peak performance of 23 frames per second for SqueezeNet on Xilinx Alveo u250 board.